Invention Grant
US07705394B2 Nonvolatile semicondutor memory with metallic silicide film electrically connected to a control gate electrode layer
失效
非易失性半导体存储器,其与金属硅化物膜电连接到控制栅电极层
- Patent Title: Nonvolatile semicondutor memory with metallic silicide film electrically connected to a control gate electrode layer
- Patent Title (中): 非易失性半导体存储器,其与金属硅化物膜电连接到控制栅电极层
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Application No.: US11553661Application Date: 2006-10-27
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Publication No.: US07705394B2Publication Date: 2010-04-27
- Inventor: Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
- Applicant: Kikuko Sugimae , Masayuki Ichige , Fumitaka Arai , Yasuhiko Matsunaga , Atsuhiro Sato
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2005-330405 20051115; JP2006-288876 20061024
- Main IPC: H01L27/115
- IPC: H01L27/115

Abstract:
A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on first, second and third source and drain regions of the memory cell transistor, low voltage transistor, and high voltage transistor, respectively.
Public/Granted literature
- US20070109848A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME Public/Granted day:2007-05-17
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