Invention Grant
- Patent Title: Switching control circuit with reduced dead time
- Patent Title (中): 切换控制电路,减少死区时间
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Application No.: US11130259Application Date: 2005-05-17
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Publication No.: US07705638B2Publication Date: 2010-04-27
- Inventor: Katsumi Miyazaki
- Applicant: Katsumi Miyazaki
- Applicant Address: JP Chiyoda-Ku, Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Chiyoda-Ku, Tokyo
- Agency: Buchanan Ingersoll & Rooney PC
- Priority: JP2004-148780 20040519
- Main IPC: H03K3/00
- IPC: H03K3/00

Abstract:
A switching control circuit of synchronous rectification type that is capable of reducing dead time is obtained. Upon detection that an output potential rises above VDD-Va, a first sensor outputs an H signal to a first input terminal of a first NOR circuit, and the first NOR circuit outputs an L signal to a second input terminal of a second NOR circuit, and the second NOR circuit outputs an H signal to a first gate driving circuit. A PMOS is thereby turned on. Upon detection that the output potential falls below GND+Vb, a second sensor outputs an L signal to a first input terminal of a first NAND circuit, and the first NAND circuit outputs an H signal to a second input terminal of a second NAND circuit, and the second NAND circuit outputs an L signal to a second gate driving circuit. An NMOS is thereby turned on.
Public/Granted literature
- US20050258890A1 Switching control circuit with reduced dead time Public/Granted day:2005-11-24
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