Invention Grant
- Patent Title: Delay locked loop circuit
- Patent Title (中): 延时锁定回路电路
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Application No.: US12033707Application Date: 2008-02-19
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Publication No.: US07705645B2Publication Date: 2010-04-27
- Inventor: Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
- Applicant: Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: McDermott Will & Emery LLP
- Priority: JP2005-033625 20050209; JP2005-264131 20050912
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
Public/Granted literature
- US20080303567A1 DELAY LOCKED LOOP CIRCUIT Public/Granted day:2008-12-11
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