Invention Grant
- Patent Title: Current mirror circuit having drain-source voltage clamp
- Patent Title (中): 电流镜电路具有漏源电压钳位
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Application No.: US12204287Application Date: 2008-09-04
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Publication No.: US07705664B2Publication Date: 2010-04-27
- Inventor: Qiang Tang
- Applicant: Qiang Tang
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
A circuit and method for providing an output current that includes biasing an output transistor in accordance with a reference current to conduct the output current and further includes maintaining a voltage across the output transistor. One embodiment includes conducting a reference current through a diode-coupled first field-effect transistor (FET) and biasing a gate of a second FET matched to the diode-coupled first FET by a voltage equal to a gate voltage of the diode-coupled first FET. A current equal to the reference current is conducted through a third FET having a gate coupled to a drain of the second FET, the third FET matched to the second FET.
Public/Granted literature
- US20090001959A1 CURRENT MIRROR CIRCUIT HAVING DRAIN-SOURCE VOLTAGE CLAMP Public/Granted day:2009-01-01
Information query
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