A static random access memory (“SRAM”) comprising: a pair of inverters each having an input and an output; a cross-coupling path coupling the input of a first inverter to the output of a second inverter; and a transmission gate, wherein the transmission gate comprises a p-channel transistor coupling the input of the second inverter to the output of the first inverter; and an n-channel transistor coupling the input of the second inverter to the output of the first inverter in parallel with the p-channel transistor. In another embodiment, the SRAM comprises a first inverter having a supply voltage node connected to a supply voltage, and a ground node connected to ground; a second inverter cross-coupled with the first inverter and having a supply voltage node connected to a supply voltage, and a ground node; and a switch selectively connecting and disconnecting the ground node of the second inverter to ground.