Invention Grant
US07706176B2 Integrated circuit, cell arrangement, method for manufacturing an integrated circuit and for reading a memory cell status, memory module
失效
集成电路，单元布置，集成电路的制造方法和用于读取存储单元状态的存储器模块
- Patent Title: Integrated circuit, cell arrangement, method for manufacturing an integrated circuit and for reading a memory cell status, memory module
- Patent Title (中): 集成电路，单元布置，集成电路的制造方法和用于读取存储单元状态的存储器模块
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Application No.: US11970302Application Date: 2008-01-07
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Publication No.: US07706176B2Publication Date: 2010-04-27
- Inventor: Rok Dittrich
- Applicant: Rok Dittrich
- Applicant Address: DE Munich FR Corbeil Essonnes
- Assignee: Qimonda AG,Altis Semiconductor, SNC
- Current Assignee: Qimonda AG,Altis Semiconductor, SNC
- Current Assignee Address: DE Munich FR Corbeil Essonnes
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
An integrated circuit having a cell arrangement is provided. The cell arrangement may include a memory cell and a reference cell. The memory cell has a first memory cell status and a second memory cell status. The reference cell is set to an intermediate memory cell status between the first memory cell status and the second memory cell status.
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