Invention Grant
- Patent Title: Reading circuitry in memory
- Patent Title (中): 在内存中读取电路
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Application No.: US11783334Application Date: 2007-04-09
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Publication No.: US07706185B2Publication Date: 2010-04-27
- Inventor: Chung-Kuang Chen
- Applicant: Chung-Kuang Chen
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Rabin & Berdo, P.C.
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A reading circuit in a memory having a first memory cell coupled to a first bit line and a second bit line and a second memory cell coupled to the second bit line and a third bit line, is provided. The reading circuitry comprises a source side sensing circuit, a drain side bias circuit, a first selection circuit and a second selection circuit. The drain side bias circuit provides a drain side bias. The first selection circuit connects the second bit line and the third bit line to the drain side bias circuit in a read operation mode. The second selection circuit connects the first bit line to the source side sensing circuit so that a source current of the first memory cell is sensed.
Public/Granted literature
- US20080247244A1 Reading circuitry in memory Public/Granted day:2008-10-09
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