A data transfer request of a data pro cessing device with respect to a synchronous memory is divided by a burst transfer length unit request dividing section into a plurality of data transfer requests in which a data transfer amount is an amount of data to be burst-transferred at a time and the data to be burst-transferred at a time is within a single memory bank. An assembling section assembles the divided data transfer requests into a plurality of new data transfer requests obtained by combining the divided data transfer requests, one for each memory bank. A data processing device can efficiently access continuous data stored in a plurality of memory banks, and is useful as a memory access control circuit of controlling an access operation of a data processing device with respect to a synchronous memory.