Invention Grant
US07707397B2 Variable group associativity branch target address cache delivering multiple target addresses per cache line 有权
每个缓存行提供多个目标地址的变量组关联分支目标地址缓存

Variable group associativity branch target address cache delivering multiple target addresses per cache line
Abstract:
A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single target address of a different previously executed branch instruction. For some groups, the four entries cache target addresses for one branch instruction in each of four different cache lines, to obtain four-way group associativity; for other groups, the four entries cache target addresses for one branch instruction in each of two different cache lines and two branch instructions in a third different cache line, to effectively obtain three-way group associativity, depending on the distribution of the branch instructions in the program. The apparatus trades off associativity for number of predictable branches per cache line on an index-by-index basis to efficiently use storage space.
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