Invention Grant
US07707397B2 Variable group associativity branch target address cache delivering multiple target addresses per cache line
有权
每个缓存行提供多个目标地址的变量组关联分支目标地址缓存
- Patent Title: Variable group associativity branch target address cache delivering multiple target addresses per cache line
- Patent Title (中): 每个缓存行提供多个目标地址的变量组关联分支目标地址缓存
-
Application No.: US11181210Application Date: 2005-07-14
-
Publication No.: US07707397B2Publication Date: 2010-04-27
- Inventor: G. Glenn Henry , Thomas C. McDonald
- Applicant: G. Glenn Henry , Thomas C. McDonald
- Applicant Address: TW Taipei
- Assignee: VIA Technologies, Inc.
- Current Assignee: VIA Technologies, Inc.
- Current Assignee Address: TW Taipei
- Agent E. Alan Davis; James W. Huffman
- Main IPC: G06F7/48
- IPC: G06F7/48 ; G06F9/00 ; G06F9/44

Abstract:
A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single target address of a different previously executed branch instruction. For some groups, the four entries cache target addresses for one branch instruction in each of four different cache lines, to obtain four-way group associativity; for other groups, the four entries cache target addresses for one branch instruction in each of two different cache lines and two branch instructions in a third different cache line, to effectively obtain three-way group associativity, depending on the distribution of the branch instructions in the program. The apparatus trades off associativity for number of predictable branches per cache line on an index-by-index basis to efficiently use storage space.
Public/Granted literature
Information query