Invention Grant
US07707435B2 Method and system for safe and efficient chip power down drawing minimal current when a device is not enabled 有权
安全高效的芯片掉电的方法和系统在器件未使能时最小化电流

Method and system for safe and efficient chip power down drawing minimal current when a device is not enabled
Abstract:
Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.
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