Invention Grant
US07709279B2 Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events during testing, and methods for fabricating inserts for use in testing semiconductor devices 有权
用于测试半导体器件的方法,用于在测试期间保护其免受静电放电事件的方法,以及用于制造用于测试半导体器件的插入件的方法

  • Patent Title: Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events during testing, and methods for fabricating inserts for use in testing semiconductor devices
  • Patent Title (中): 用于测试半导体器件的方法,用于在测试期间保护其免受静电放电事件的方法,以及用于制造用于测试半导体器件的插入件的方法
  • Application No.: US10827806
    Application Date: 2004-04-20
  • Publication No.: US07709279B2
    Publication Date: 2010-05-04
  • Inventor: David R. HembreeSalman Akram
  • Applicant: David R. HembreeSalman Akram
  • Applicant Address: US ID Boise
  • Assignee: Micron Technology, Inc.
  • Current Assignee: Micron Technology, Inc.
  • Current Assignee Address: US ID Boise
  • Agency: TraskBritt
  • Main IPC: H01L21/66
  • IPC: H01L21/66 H01L23/58
Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events during testing, and methods for fabricating inserts for use in testing semiconductor devices
Abstract:
An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD protection, are provided. An ESD structure may be associated with each interconnect, either individually or shared between two or more interconnects. Each interconnect includes a contact tip for establishing a temporary electrical connection with a bond pad of the semiconductor device and a contact pad for electrically interfacing the bond pad with external burn-in and/or test equipment. The ESD structure may be implemented, for example, as a fusible element or a shunting element, such as a pair of diodes, a diode-resistor network, or a pair of transistors. The interconnect may be employed as part of an insert including a plurality of interconnects that provides ESD protection to a plurality of integrated circuits of at least one semiconductor device.
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