Invention Grant
- Patent Title: Hierarchical 2T-DRAM with self-timed sensing
- Patent Title (中): 具有自定时感测功能的分层2T-DRAM
-
Application No.: US12198969Application Date: 2008-08-27
-
Publication No.: US07709299B2Publication Date: 2010-05-04
- Inventor: Richard E. Matick , Stanley E. Schuster
- Applicant: Richard E. Matick , Stanley E. Schuster
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent Ken Corsello
- Main IPC: H01L21/82
- IPC: H01L21/82

Abstract:
An embodiment of the present invention is method of forming an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.
Public/Granted literature
- US20080308941A1 HIERARCHICAL 2T-DRAM WITH SELF-TIMED SENSING Public/Granted day:2008-12-18
Information query
IPC分类: