Invention Grant
US07709317B2 Method to increase strain enhancement with spacerless FET and dual liner process
失效
用无衬垫FET和双衬垫工艺增加应变增强的方法
- Patent Title: Method to increase strain enhancement with spacerless FET and dual liner process
- Patent Title (中): 用无衬垫FET和双衬垫工艺增加应变增强的方法
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Application No.: US11164193Application Date: 2005-11-14
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Publication No.: US07709317B2Publication Date: 2010-05-04
- Inventor: Haining S. Yang , Siddhartha Panda
- Applicant: Haining S. Yang , Siddhartha Panda
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent H. Daniel Schnurmann
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/84

Abstract:
A semiconductor structure and a method of fabricating the same in which strain enhancement is achieved for both nFET and pFET devices is provided. In particular, the present invention provides at least one spacerless FET for stronger strain enhancement and defect reduction. The at least one spacerless FET can be a pFET, an nFET, or a combination thereof, with spacerless pFETs being particularly preferred since pFETs are generally fabricated to have a greater width than nFETs. The at least one spacerless FET allows to provide a stress inducing liner in closer proximity to the device channel than prior art structures including FETs having spacers. The spacerless FET is achieved without negatively affecting the resistance of the corresponding silicided source/drain diffusion contacts, which do not encroach underneath the spacerless FET.
Public/Granted literature
- US20070108525A1 STRUCTURE AND METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS Public/Granted day:2007-05-17
Information query
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