A first gate, formed on a substrate, is surmounted by a hard layer designed, with first spacers surrounding the first gate, to act as etching mask to bound the channel and a pad that bounds a space subsequently used to form a gate cavity. The hard layer is preferably made of silicon nitride. Before flipping and bonding, a bounding layer, preferably made of amorphous silicon or polysilicon, is formed to bound drain and source areas. After flipping and bonding of the assembly on a second substrate, a second gate is formed in the gate cavity. At least partial silicidation of the bounding layer is then performed before the metal source and drain electrodes are produced.