Invention Grant
US07709927B2 Shallow trench isolation structures for semiconductor devices including wet etch barriers
有权
用于包括湿蚀刻障碍物的半导体器件的浅沟槽隔离结构
- Patent Title: Shallow trench isolation structures for semiconductor devices including wet etch barriers
- Patent Title (中): 用于包括湿蚀刻障碍物的半导体器件的浅沟槽隔离结构
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Application No.: US12123817Application Date: 2008-05-20
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Publication No.: US07709927B2Publication Date: 2010-05-04
- Inventor: Dong-suk Shin , Il-young Yoon , Yong-kuk Jeong , Jung-shik Heo
- Applicant: Dong-suk Shin , Il-young Yoon , Yong-kuk Jeong , Jung-shik Heo
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2007-0049960 20070522
- Main IPC: H01L21/76
- IPC: H01L21/76

Abstract:
A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge regions of both end portions of the sidewall oxide layer so as to extend from an entry of the trench adjacent to an upper surface of the substrate to the nitride liner. A dent filling insulating layer is provided on the nitride liner in the trench to protect a surface of the first impurity doped oxide layer. Related methods are also disclosed.
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