Invention Grant
- Patent Title: Semiconductor wafer having a separation portion on a peripheral area
- Patent Title (中): 半导体晶片在周边区域具有分离部分
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Application No.: US11245059Application Date: 2005-10-07
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Publication No.: US07709932B2Publication Date: 2010-05-04
- Inventor: Yoshihiko Nemoto , Masahiro Sunohara , Kenji Takahashi
- Applicant: Yoshihiko Nemoto , Masahiro Sunohara , Kenji Takahashi
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2003-189574 20030701
- Main IPC: H01L29/06
- IPC: H01L29/06

Abstract:
A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.
Public/Granted literature
- US20060038260A1 Semiconductor wafer and method of manufacturing semiconductor device Public/Granted day:2006-02-23
Information query
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