Invention Grant
- Patent Title: Semiconductor package, including connected upper and lower interconnections
- Patent Title (中): 半导体封装，包括上下互连
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Application No.: US10860478Application Date: 2004-06-02
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Publication No.: US07709942B2Publication Date: 2010-05-04
- Inventor: Hiroyasu Jobetto
- Applicant: Hiroyasu Jobetto
- Applicant Address: JP Tokyo JP Tokyo
- Assignee: Casio Computer Co., Ltd.,CMK Corporation
- Current Assignee: Casio Computer Co., Ltd.,CMK Corporation
- Current Assignee Address: JP Tokyo JP Tokyo
- Agency: Frishhauf, Holtz, Goodman & Chick, P.C.
- Priority: JP2003-158489 20030603
- Main IPC: H01L23/02
- IPC: H01L23/02
Abstract:
A semiconductor package includes a base plate, at least one semiconductor constructing body which is formed on one surface of the base plate and has a plurality of external connection electrodes formed on a semiconductor substrate, an insulating layer which is formed on one surface of the base plate around the semiconductor constructing body, upper interconnections which are formed on the insulating layer and each includes at least one interconnection layer, at least some of the upper interconnections are connected to the external connection electrodes of the semiconductor constructing body, lower interconnections which are formed on the other surface of the base plate and each includes at least one interconnection layer, and at least some of the lower interconnections which are electrically connected to the upper interconnections.
Public/Granted literature
- US20040245614A1 Semiconductor package having semiconductor constructing body and method of manufacturing the same Public/Granted day:2004-12-09
Information query
IPC分类:
