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US07709954B2 Redistribution layer for wafer-level chip scale package and method therefor 有权
晶圆级芯片级封装的再分配层及其方法

  • Patent Title: Redistribution layer for wafer-level chip scale package and method therefor
  • Patent Title (中): 晶圆级芯片级封装的再分配层及其方法
  • Application No.: US12090686
    Application Date: 2006-10-18
  • Publication No.: US07709954B2
    Publication Date: 2010-05-04
  • Inventor: Michael C. Loo
  • Applicant: Michael C. Loo
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Agent Peter Zawilski
  • International Application: PCT/IB2006/053840 WO 20061018
  • International Announcement: WO2007/046062 WO 20070426
  • Main IPC: H01L23/48
  • IPC: H01L23/48 ;  H01L21/44
Redistribution layer for wafer-level chip scale package and method therefor
Abstract:
In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has atop (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined (35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern. The second organic dielectric layer is removed (50) from the bump pad connections exposing the bump pads (330).
Abstract(Chinese):

在一个示例性实施例中，存在一种在晶片级芯片级（WLCS）封装（300）中封装具有电路图案（305）的集成电路器件（IC）的方法。 该方法包括在第一介电层（315）上沉积金属层（5,10,15）和在接合焊盘开口（310）和凸块焊盘开口（330）中填充（20）; 金属层（360）具有顶部（340）和底部（360）层。 在金属层（360）中，通过除了在接合焊盘开口（310）和焊盘开口（310）之外的区域中去除金属的顶层来限定焊盘连接（310）和焊盘焊盘连接（330） （330），并且在没有接合焊盘或凸块焊盘连接的区域中离开金属的底层（360）。 在底部金属层中，限定了接合焊盘和凸块焊盘之间的连接迹线（35,40）。 在硅衬底（305）上沉积第二有机介电层（325）（45），其包围电路图案。 第二有机电介质层从暴露焊盘（330）的凸块焊盘连接件移除（50）。

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