Invention Grant
US07710169B2 Semiconductor integrated circuit controlling output impedance and slew rate
失效
半导体集成电路控制输出阻抗和转换速率
- Patent Title: Semiconductor integrated circuit controlling output impedance and slew rate
- Patent Title (中): 半导体集成电路控制输出阻抗和转换速率
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Application No.: US11876231Application Date: 2007-10-22
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Publication No.: US07710169B2Publication Date: 2010-05-04
- Inventor: Yoshihiro Tanaka
- Applicant: Yoshihiro Tanaka
- Applicant Address: JP Kanagawa
- Assignee: NEC Electronics Corporation
- Current Assignee: NEC Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2006-285853 20061020
- Main IPC: H03K3/00
- IPC: H03K3/00 ; H03B1/00

Abstract:
A semiconductor integrated circuit according to the invention has a plurality of output transistors connected to an output terminal through which output data is outputted, and an impedance control circuit and a slew rate control circuit. The impedance control circuit generates control signals specifying output transistors to be turned on when the output data is output, from among the plurality of output transistors. The slew rate control circuit generates, according to the control signals, drive signals driving the output transistors to be turned on, and variably sets respective delay times of the drive signals according to the control signals.
Public/Granted literature
- US20080094112A1 SEMICONDUCTOR INTEGRATED CIRCUIT CONTROLLING OUTPUT IMPEDANCE AND SLEW RATE Public/Granted day:2008-04-24
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