Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage.