Invention Grant
- Patent Title: Latch device having low-power data retention
- Patent Title (中): 具有低功率数据保持的锁存器件
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Application No.: US11854088Application Date: 2007-09-12
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Publication No.: US07710177B2Publication Date: 2010-05-04
- Inventor: Andrew P. Hoover
- Applicant: Andrew P. Hoover
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H03K3/00
- IPC: H03K3/00

Abstract:
A latch of an integrated circuit is able to retain data at the latch when the integrated circuit is in a low-power mode. The latch retains data at a retention stage in response to assertion of an isolation signal. In response to a reference voltage supplied to the latch being restored to a normal operating voltage, indicating that the integrated circuit has transitioned from the low-power mode to a normal mode, a data restoration circuit provides the retained data at the output of the latch prior to negation of the isolation signal. This reduces the likelihood that a delay in negation of the isolation signal will result in the latch output providing incorrect data, thereby reducing the likelihood of the latch output causing errors in downstream elements of the integrated circuit.
Public/Granted literature
- US20090066385A1 LATCH DEVICE HAVING LOW-POWER DATA RETENTION Public/Granted day:2009-03-12
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