In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of memory cells arranged into rows and columns, wherein each memory cell comprises an access transistor coupled to a storage transistor, each access transistor being arranged in a rectangular shape having a length greater than a width, the length being aligned with a corresponding column, the access transistor coupling to a storage transistor having a width greater than the width of the rectangular shape, the access transistor having a length aligned with a corresponding row such that each memory cell is L-shaped, and wherein the L-shaped memory cells in each column are staggered with respect to neighboring columns such that the L-shaped memory cells in a given column are interlocked with the L-shaped memory cells in an adjacent column.