Invention Grant
- Patent Title: System and method for verification aware synthesis
- Patent Title (中): 用于验证感知合成的系统和方法
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Application No.: US11324169Application Date: 2005-12-30
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Publication No.: US07711536B2Publication Date: 2010-05-04
- Inventor: Michael McNamara
- Applicant: Michael McNamara
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agent Stephen C. Durant
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/445
Abstract:
A method of synthesis of a model representing a design of an integrated circuit is provided including associating a test environment with a first model representing a design of an integrated circuit; translating the first model of the design to a second model of the design; and automatically generating an adaptor that adapts the second model to the test environment.
Public/Granted literature
- US20070156378A1 System and method for verification aware synthesis Public/Granted day:2007-07-05
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