Invention Grant
- Patent Title: Trap-based mechanism for tracking accesses of logical components
- Patent Title (中): 用于跟踪逻辑组件访问的基于陷阱的机制
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Application No.: US11206492Application Date: 2005-08-17
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Publication No.: US07711937B1Publication Date: 2010-05-04
- Inventor: Nedim Fresko , Dean R. Long , Jiangli Zhou
- Applicant: Nedim Fresko , Dean R. Long , Jiangli Zhou
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle America, Inc.
- Current Assignee: Oracle America, Inc.
- Current Assignee Address: US CA Redwood Shores
- Agency: Osha • Liang LLP
- Main IPC: G06F9/00
- IPC: G06F9/00

Abstract:
A trap-based mechanism is provided for gaining greater visibility into the memory usage of a process. To detect and record the memory accesses of a process, a virtual address range (or a plurality of address ranges) of the process is set to a protected status. This address range represents the range of virtual addresses that are to be monitored for access. By setting the address range to a protected status, whenever a memory access (in one implementation, whenever a memory write) is made to a virtual address within that address range, a trap arises. When the trap arises, a trap handler is invoked. When invoked, the trap handler records the virtual address that was accessed. In this manner, the access of the virtual address is detected and recorded without having to add extensive instrumentation code to the process.
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