Invention Grant
- Patent Title: ATE architecture and method for DFT oriented testing
- Patent Title (中): ATE架构和DFT面向测试方法
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Application No.: US11589465Application Date: 2006-10-30
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Publication No.: US07712000B2Publication Date: 2010-05-04
- Inventor: Ajay Khoche , Klaus-Dieter Hilliges
- Applicant: Ajay Khoche , Klaus-Dieter Hilliges
- Applicant Address: SG Singapore
- Assignee: Verigy (Singapore) Pte. Ltd.
- Current Assignee: Verigy (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Holland & Hart, LLP
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK couples the hardware resources and software processes as needed for a first DFT testing block to be enabled for testing only when such resources and processes are available and locked for the first DFT testing block. The DPK is coupled to the first DFT testing blocks via data channels and control channels that are selected as needed for having the first DFT testing block enabled for testing. The channels are under the control of an DUTs-ATE interface which is directed by the DPK for connecting the first DFT testing block to the locked hardware resource and the locked software processes. Each set up process corresponding to any subsequent DFT testing block requesting any hardware resource and any software processes that are already locked for use is paused until such locked resource and locked software processes are unlocked and assigned for having that subsequent DFT testing block enabled for testing.
Public/Granted literature
- US20080104461A1 ATE architecture and method for DFT oriented testing Public/Granted day:2008-05-01
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