Invention Grant
- Patent Title: Semiconductor integrated circuit and method of testing semiconductor integrated circuit
- Patent Title (中): 半导体集成电路和半导体集成电路测试方法
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Application No.: US11358135Application Date: 2006-02-22
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Publication No.: US07712001B2Publication Date: 2010-05-04
- Inventor: Itsuo Hidaka , Tsuneki Sasaki
- Applicant: Itsuo Hidaka , Tsuneki Sasaki
- Applicant Address: JP Kawasaki, Kanagawa
- Assignee: NEC Electronics Corporation
- Current Assignee: NEC Electronics Corporation
- Current Assignee Address: JP Kawasaki, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2005-047967 20050223
- Main IPC: G01R31/28
- IPC: G01R31/28 ; H03K19/00

Abstract:
A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit outputting an external output data and a third combinational circuit; a first selection circuit; and a second selection circuit. The first selection circuit receives the external input data and a stored data held by the first memory element, and outputs any of them to the first combinational circuit. The second selection circuit receives the external output data output from the second combinational circuit and an operation result data output from the third combinational circuit, and outputs any of them to the second memory element.
Public/Granted literature
- US20060190786A1 Semiconductor integrated circuit and method of tesiting semiconductor integrated circuit Public/Granted day:2006-08-24
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