When memory cells enter an operation mode which performs only data holding, a control circuit controls the memory cells and an ECC circuit as follows. A plurality of data are read out to generate and store a check bit for error detection and correction. Refreshing is performed in a period within the error occurrence allowable range of an error correcting operation performed by the ECC circuit by using the check bit. Before a normal operation mode is restored from the operation mode which performs only data holding, an error bit of the data is corrected by using the check bit. In an entry/exit period, read/write and an ECC operation are sequentially performed for all the memory cells by a page mode operation. Memory cells connected to a word line which is not accessed by the page mode operation are sequentially activated and refreshed.