Invention Grant
US07712061B2 Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits
有权
用于在集成电路设计中生成和验证隔离逻辑模块的方法，系统和计算机程序产品
- Patent Title: Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits
- Patent Title (中): 用于在集成电路设计中生成和验证隔离逻辑模块的方法，系统和计算机程序产品
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Application No.: US11959427Application Date: 2007-12-18
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Publication No.: US07712061B2Publication Date: 2010-05-04
- Inventor: Bhanu Kapoor , Debabrata Bagchi , Sanjay Churiwala
- Applicant: Bhanu Kapoor , Debabrata Bagchi , Sanjay Churiwala
- Applicant Address: US CA San Jose
- Assignee: ATRENTA, Inc.
- Current Assignee: ATRENTA, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Sughrue Mion, PLLC
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.
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