Invention Grant
US07714429B2 Wafer structure with a plurality of functional macro chips for chip-on-chip configuration
失效
晶圆结构具有多个用于片上芯片配置的功能宏芯片
- Patent Title: Wafer structure with a plurality of functional macro chips for chip-on-chip configuration
- Patent Title (中): 晶圆结构具有多个用于片上芯片配置的功能宏芯片
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Application No.: US11528323Application Date: 2006-09-28
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Publication No.: US07714429B2Publication Date: 2010-05-11
- Inventor: Shouji Sakuma , Yoshiyuki Ishida
- Applicant: Shouji Sakuma , Yoshiyuki Ishida
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Yokohama
- Priority: JP2006-085702 20060327
- Main IPC: H01L23/02
- IPC: H01L23/02
Abstract:
A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.
Public/Granted literature
- US20070222045A1 Semiconductor device for chip-on-chip configuration and method for manufacturing the same Public/Granted day:2007-09-27
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