Invention Grant
- Patent Title: Integrated circuit for scan driving
- Patent Title (中): 用于扫描驱动的集成电路
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Application No.: US10717235Application Date: 2003-11-18
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Publication No.: US07714827B2Publication Date: 2010-05-11
- Inventor: Yasushi Kubota , Seiji Murakami
- Applicant: Yasushi Kubota , Seiji Murakami
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent William B. Kempler; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Priority: JP2002-348991 20021129
- Main IPC: G09G3/36
- IPC: G09G3/36

Abstract:
An integrated circuit is provided for scan driving that can significantly reduce the chip size. In first region AODD, odd-numbered output pads OUT1, OUT3, . . . OUT173, OUT175, driver circuits DR1, DR3, . . . DR173, DR175, and flip-flops SREG1, SREG3, . . . SREG173, SREG175 in an order corresponding to the order of the odd-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction). In second region AEVEN, even-numbered output pads OUT2, OUT4, . . . OUT174, OUT176, driver circuits DR2, DR4, . . . DR174, DR176, and flip-flops SREG2, SREG4, . . . SREG174, SREG176 in an order corresponding to the order of the even-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction).
Public/Granted literature
- US20040160432A1 Integrated circuit for scan driving Public/Granted day:2004-08-19
Information query
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