Invention Grant
- Patent Title: Intelligent inspection based on test chip probe failure maps
- Patent Title (中): 基于测试芯片探针故障图的智能检测
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Application No.: US11853615Application Date: 2007-09-11
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Publication No.: US07715997B2Publication Date: 2010-05-11
- Inventor: Garrett John Long , Saju Francis Olakengil , Pramod Gaud , John Jacob Roberts
- Applicant: Garrett John Long , Saju Francis Olakengil , Pramod Gaud , John Jacob Roberts
- Applicant Address: US CA San Jose
- Assignee: KLA-Tencor Technologies Corporation
- Current Assignee: KLA-Tencor Technologies Corporation
- Current Assignee Address: US CA San Jose
- Agency: JDI Patent
- Agent Joshua D. Isenberg
- Main IPC: G06F19/00
- IPC: G06F19/00 ; G06F11/00 ; G01B21/30 ; G01N21/88
Abstract:
A method and system for semiconductor wafer inspection is disclosed. Each of a plurality of dies on a wafer may be probed with a probe tool to produce probe data. The probe data may be used to generate one or more non-repeating care areas. An inspection tool may use the non-repeating care areas to perform an inspection of the semiconductor wafer.
Public/Granted literature
- US20090070055A1 INTELLIGENT INSPECTION BASED ON TEST CHIP PROBE FAILURE MAPS Public/Granted day:2009-03-12
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