Invention Grant
US07716268B2 Method and apparatus for providing a processor based nested form polynomial engine
有权
用于提供基于处理器的嵌套形式多项式引擎的方法和装置
- Patent Title: Method and apparatus for providing a processor based nested form polynomial engine
- Patent Title (中): 用于提供基于处理器的嵌套形式多项式引擎的方法和装置
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Application No.: US11072211Application Date: 2005-03-04
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Publication No.: US07716268B2Publication Date: 2010-05-11
- Inventor: Jeffrey J. Dobbek , Kirk Hwang
- Applicant: Jeffrey J. Dobbek , Kirk Hwang
- Applicant Address: NL Amsterdam
- Assignee: Hitachi Global Storage Technologies Netherlands B.V.
- Current Assignee: Hitachi Global Storage Technologies Netherlands B.V.
- Current Assignee Address: NL Amsterdam
- Agency: Merchant & Gould
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F1/02

Abstract:
A method and apparatus for providing a processor based nested form polynomial engine are disclosed. A concise instruction format is provided to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine. The instruction causing a processor to set coefficient and data address pointers for evaluating a polynomial, to load loading a coefficient and data operand into a coefficient register and a data register, respectively, to multiply the contents of the coefficient register and data register to produce a product, to add a next coefficient operand to the product to produce a sum, to provide the sum to an accumulator and to repeat the loading, multiplying, adding and providing until evaluation of the polynomial is complete.
Public/Granted literature
- US20060200732A1 Method and apparatus for providing a processor based nested form polynomial engine Public/Granted day:2006-09-07
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