Invention Grant
US07716442B2 Interfacing processors with external memory supporting burst mode
有权
接口处理器与支持突发模式的外部存储器
- Patent Title: Interfacing processors with external memory supporting burst mode
- Patent Title (中): 接口处理器与支持突发模式的外部存储器
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Application No.: US10489800Application Date: 2002-09-17
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Publication No.: US07716442B2Publication Date: 2010-05-11
- Inventor: Eugene Pascal Herczog
- Applicant: Eugene Pascal Herczog
- Applicant Address: KY TW Shenzen FR Issy les Mouineaux TW
- Assignee: MStar Semiconductor, Inc.,MStar Software R&D, Ltd.,MStar France SAS,MStar Semiconductor, Inc.
- Current Assignee: MStar Semiconductor, Inc.,MStar Software R&D, Ltd.,MStar France SAS,MStar Semiconductor, Inc.
- Current Assignee Address: KY TW Shenzen FR Issy les Mouineaux TW
- Agency: Edell, Shapiro & Finnan, LLC
- Priority: GB0122401.3 20010917
- International Application: PCT/GB02/04216 WO 20020917
- International Announcement: WO03/025768 WO 20030327
- Main IPC: G06F13/14
- IPC: G06F13/14
Abstract:
Multiple data devices (A,B,C) are interfaced via a bus arbiter (S) with an external memory (F) so as to support burst-mode access by each device (A,B,C) one or more read registers (R1,R2,R3) are provided in the memory (F), and each register (R1,R2,R3) supports burst-mode access by a corresponding device (A,B,C). The arbiter (s) selects the register to be used following the initial access burst, according to the device requiring access. Thus, the memory (F) supports multiple burst-mode accesses in parallel.
Public/Granted literature
- US20050005035A1 Interfacing processors with external memory supporting burst mode Public/Granted day:2005-01-06
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