Invention Grant
US07716460B2 Effective use of a BHT in processor having variable length instruction set execution modes
有权
在具有可变长度指令集执行模式的处理器中有效使用BHT
- Patent Title: Effective use of a BHT in processor having variable length instruction set execution modes
- Patent Title (中): 在具有可变长度指令集执行模式的处理器中有效使用BHT
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Application No.: US11536743Application Date: 2006-09-29
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Publication No.: US07716460B2Publication Date: 2010-05-11
- Inventor: Brian Michael Stempel , Rodney Wayne Smith
- Applicant: Brian Michael Stempel , Rodney Wayne Smith
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agent Nicholas J. Pauley; Peter Kamarchik; Sam Talpalatsky
- Main IPC: G06F7/38
- IPC: G06F7/38 ; G06F9/00 ; G06F9/44 ; G06F15/00
Abstract:
In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.
Public/Granted literature
- US20080082807A1 Effective Use of a BHT in Processor Having Variable Length Instruction Set Execution Modes Public/Granted day:2008-04-03
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