Invention Grant
- Patent Title: Dynamic timing adjustment in a circuit device
- Patent Title (中): 电路设备中的动态时序调整
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Application No.: US11371142Application Date: 2006-03-08
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Publication No.: US07716511B2Publication Date: 2010-05-11
- Inventor: Anis M. Jarrar , Colin MacDonald
- Applicant: Anis M. Jarrar , Colin MacDonald
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G06F1/12
- IPC: G06F1/12 ; H04L7/00

Abstract:
A method includes determining a first operational characteristic representative of an operational speed of a circuit device at a first time. The method further includes receiving an input signal at an input of a first latch of the circuit device and receiving an output signal at an input of a second latch of the circuit device. The method additionally includes delaying a clock signal by a first delay to provide a first adjusted clock signal and delaying the clock signal by a second delay to provide a second adjusted clock signal. In one embodiment, the first delay and the second delay are based on the first operational characteristic. The method further includes latching the input signal at the first latch responsive to the first adjusted clock signal and latching the output signal at the second latch responsive to the second adjusted clock signal.
Public/Granted literature
- US20070214377A1 Dynamic timing adjustment in a circuit device Public/Granted day:2007-09-13
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