Invention Grant
US07716542B2 Programmable memory built-in self-test circuit and clock switching circuit thereof
有权
可编程存储器内置自检电路及其时钟切换电路
- Patent Title: Programmable memory built-in self-test circuit and clock switching circuit thereof
- Patent Title (中): 可编程存储器内置自检电路及其时钟切换电路
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Application No.: US11939282Application Date: 2007-11-13
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Publication No.: US07716542B2Publication Date: 2010-05-11
- Inventor: Yeong-Jar Chang , Chung-Fu Lin
- Applicant: Yeong-Jar Chang , Chung-Fu Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Faraday Technology Corp.
- Current Assignee: Faraday Technology Corp.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G11C29/00 ; G06F11/00

Abstract:
A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.
Public/Granted literature
- US20090125763A1 PROGRAMMABLE MEMORY BUILT-IN SELF-TEST CIRCUIT AND CLOCK SWITCHING CIRCUIT THEREOF Public/Granted day:2009-05-14
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