Invention Grant
US07716617B2 Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device
失效
半导体器件,制造图案布局的方法,制造掩模图案的方法,制作布局的方法,制造光掩模的方法,光掩模和半导体器件的制造方法
- Patent Title: Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device
- Patent Title (中): 半导体器件,制造图案布局的方法,制造掩模图案的方法,制作布局的方法,制造光掩模的方法,光掩模和半导体器件的制造方法
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Application No.: US11299843Application Date: 2005-12-13
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Publication No.: US07716617B2Publication Date: 2010-05-11
- Inventor: Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
- Applicant: Hiromitsu Mashita , Toshiya Kotani , Atsushi Maesono , Ayako Nakano , Tadahito Fujisawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Tosbhia
- Current Assignee: Kabushiki Kaisha Tosbhia
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2004-360109 20041213; JP2005-047461 20050223
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K19/177 ; H01L25/00

Abstract:
A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.
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