Invention Grant
US07718482B2 CD gate bias reduction and differential N+ poly doping for CMOS circuits
有权
用于CMOS电路的CD栅偏压减小和差分N +多掺杂
- Patent Title: CD gate bias reduction and differential N+ poly doping for CMOS circuits
- Patent Title (中): 用于CMOS电路的CD栅偏压减小和差分N +多掺杂
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Application No.: US11928872Application Date: 2007-10-30
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Publication No.: US07718482B2Publication Date: 2010-05-18
- Inventor: Shashank Ekbote , Borna Obradovic , Greg C. Baldwin
- Applicant: Shashank Ekbote , Borna Obradovic , Greg C. Baldwin
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/8238
- IPC: H01L21/8238
Abstract:
A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.
Public/Granted literature
- US20090098694A1 CD GATE BIAS REDUCTION AND DIFFERENTIAL N+ POLY DOPING FOR CMOS CIRCUITS Public/Granted day:2009-04-16
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