Invention Grant
US07718494B2 Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach
有权
用双阱剂量法在CMOS工艺流程中形成高漏电电压公差MOSFET晶体管的方法
- Patent Title: Method for forming high-drain-voltage tolerance MOSFET transistor in a CMOS process flow with double well dose approach
- Patent Title (中): 用双阱剂量法在CMOS工艺流程中形成高漏电电压公差MOSFET晶体管的方法
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Application No.: US11784721Application Date: 2007-04-09
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Publication No.: US07718494B2Publication Date: 2010-05-18
- Inventor: Yung Chih Tsai , Michael Yu , Chih-Ping Chao , Chih-Sheng Chang
- Applicant: Yung Chih Tsai , Michael Yu , Chih-Ping Chao , Chih-Sheng Chang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/8234
- IPC: H01L21/8234

Abstract:
A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.
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