Invention Grant
- Patent Title: Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement
- Patent Title (中): 调谐拉伸应力低电阻率槽接触结构为n型晶体管性能提升
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Application No.: US11647977Application Date: 2006-12-29
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Publication No.: US07719062B2Publication Date: 2010-05-18
- Inventor: Kevin J. Fischer , Vinay B. Chikarmane , Brennan L. Peterson
- Applicant: Kevin J. Fischer , Vinay B. Chikarmane , Brennan L. Peterson
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/48
- IPC: H01L23/48
Abstract:
A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
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