Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
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Application No.: US11290394Application Date: 2005-12-01
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Publication No.: US07719331B2Publication Date: 2010-05-18
- Inventor: Shotaro Kobayashi
- Applicant: Shotaro Kobayashi
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2004-350103 20041202
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/087

Abstract:
Disclosed is a PLL circuit including a phase frequency detector (PFD) for comparing phase and frequency between an input signal and an output signal, a charge pump circuit for charging a capacitor when an up-signal from the PFD is activated, discharging the capacitor when a down-signal is activated, and for outputting the terminal voltage of the capacitor as a control voltage, and a VCO for outputting an output signal of a frequency in accordance with the control voltage. An output of the VCO is fed back as an output signal to the PFD as input. The PFD includes a delay adjustment circuit for exercising control for resetting the up-signal and the down-signal with a preset delay as from a time point both up-signal and the down-signal have been activated. There is also provided a comparator amplifier circuit for comparing a reference voltage, corresponding to a control voltage when both up-signal and down-signal are activated, to supply first and second control signals to the delay adjustment circuit. The pulse widths of up and down-signals are adjusted depending on current offset characteristics of the charge pump circuit.
Public/Granted literature
- US20060119405A1 PLL circuit Public/Granted day:2006-06-08
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