Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
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Application No.: US12235645Application Date: 2008-09-23
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Publication No.: US07719366B2Publication Date: 2010-05-18
- Inventor: Shinichiro Tsuda
- Applicant: Shinichiro Tsuda
- Applicant Address: JP Tokyo
- Assignee: Sony Corporation
- Current Assignee: Sony Corporation
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JPP2007-250208 20070926
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/085

Abstract:
Disclosed herein is a phase lock loop (PLL) circuit capable of executing digital control of an oscillation circuit thereof by using a dividing ratio represented by a digital value obtained by dividing an oscillation frequency by a reference frequency. The PLL circuit includes a phase comparator for comparing the digital value obtained by converting the dividing ratio with a digital value representing each cumulative addition value of a clock count expressed in a decimal-point format representing the oscillation signal in each period of a reference signal, a loop-gain control section configured to control the loop gain of the PLL circuit, and an output converging section configured to converge an output by the phase comparator.
Public/Granted literature
- US20090079508A1 PLL CIRCUIT Public/Granted day:2009-03-26
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