Invention Grant
US07721167B1 Apparatus and method for testing and debugging an integrated circuit
有权
用于集成电路测试和调试的装置和方法
- Patent Title: Apparatus and method for testing and debugging an integrated circuit
- Patent Title (中): 用于集成电路测试和调试的装置和方法
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Application No.: US12154896Application Date: 2008-05-28
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Publication No.: US07721167B1Publication Date: 2010-05-18
- Inventor: Saeed Azimi , Son Ho , Daniel Smathers
- Applicant: Saeed Azimi , Son Ho , Daniel Smathers
- Applicant Address: BE Hamilton
- Assignee: Marvell International Ltd.
- Current Assignee: Marvell International Ltd.
- Current Assignee Address: BE Hamilton
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A system for receiving Joint Task Action Group (JTAG) data bits from a device under test includes a deserializer that receives serial messages from the device under test and forms data frames based on the serial messages. A frame sync module communicates with the deserializer and forms JTAG data bits based on the data frames. N virtual JTAG test access ports (VTAPs), each having an input and an output. The N VTAPs are connected in a daisy chain and the input of a first VTAP receives the JTAG data bits from the frame sync module.
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