Invention Grant
US07721232B2 Designated MOSFET and driver design to achieve lowest parasitics in discrete circuits
有权
指定MOSFET和驱动器设计,以实现分立电路中的最低寄生效应
- Patent Title: Designated MOSFET and driver design to achieve lowest parasitics in discrete circuits
- Patent Title (中): 指定MOSFET和驱动器设计,以实现分立电路中的最低寄生效应
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Application No.: US10998471Application Date: 2004-11-29
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Publication No.: US07721232B2Publication Date: 2010-05-18
- Inventor: Jens Ejury
- Applicant: Jens Ejury
- Applicant Address: DE Munich
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Munich
- Agency: Eschweiler & Associates, LLC
- Main IPC: H03F3/38
- IPC: H03F3/38

Abstract:
Apparatus are described for a pair of MOSFET power transistors, a MOSFET driver, and an idealized circuit layout utilized in a power stage such as that of a power conversion system. The power stage comprises a pair of MOSFET transistors having substantially identical electrical characteristics and complementary package configurations for simplifying and optimizing the layout of the power stage on a single side or layer of a printed circuit board. The ideal layout effectively avoids parasitic circuit components, minimizes layout area and costs, and permits operation at higher switching frequencies. A new MOSFET transistor pin configuration is also described that is essentially a functional mirror or functional complement of an existing MOSFET transistor pin configuration to provide the complementary package configurations and the optimized PCB layout. A customized MOSFET driver pin configuration further optimizes the power stage layout by arranging the pins of the driver to coordinate with those of the MOSFET transistor pair.
Public/Granted literature
- US20060113657A1 Designated MOSFET and driver design to achieve lowest parasitics in discrete circuits Public/Granted day:2006-06-01
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