A network overclock control circuit for a computer includes an RC circuit, first and second comparator circuits, and first and second switch circuits. A signal pin of a network indicating lamp is connected to input terminals of the first and second comparator circuits via the RC circuit. Output terminals of the first and second comparator circuits are respectively connected to first and second clock pins of a clock chip via the first and second switch circuits. When network has little traffic, the first and second comparator circuits control the first and second switch circuits to output low level signals. When network has medium to high traffic, the first and second comparator circuits control the first and second switch circuits to output high and low level signals. When network is overloaded, the first and second comparator circuits control the first and second switch circuits to output high level signals.