A method of designing a low power circuit that implements specified functionality, the method including: analyzing code for an algorithmic description of the specified functionality to generate a design representation of the circuit at the algorithmic level; instrumenting the code for the algorithmic description so as to capture data streams during execution/simulation of the algorithmic description; executing/simulating the instrumented code to generate an activity profile for the algorithmic description, wherein said activity profile includes at least portions of data traces of at least a portion of the executed algorithmic description; using the design representation to generate an initial hardware design that is an estimate of hardware resources necessary to implement at least some of the specified functionality; and computing power consumption for the initial hardware design based on the activity profile and power models for the hardware resources.