Invention Grant
US07725865B2 Method, storage media storing program, and component for avoiding increase in delay time in semiconductor circuit having plural wiring layers
有权
方法，存储介质存储程序和用于避免在具有多个布线层的半导体电路中延迟时间增加的部件
- Patent Title: Method, storage media storing program, and component for avoiding increase in delay time in semiconductor circuit having plural wiring layers
- Patent Title (中): 方法，存储介质存储程序和用于避免在具有多个布线层的半导体电路中延迟时间增加的部件
-
Application No.: US11236532Application Date: 2005-09-28
-
Publication No.: US07725865B2Publication Date: 2010-05-25
- Inventor: Hisayoshi Oba
- Applicant: Hisayoshi Oba
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Microelectronics Limited
- Current Assignee: Fujitsu Microelectronics Limited
- Current Assignee Address: JP Yokohama
- Agency: Staas & Halsey LLP
- Priority: JP2005-096133 20050329
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K17/693 ; H01L23/02 ; H01L29/04 ; H01L29/40
Abstract:
A method for a computer setting up a terminal layer of a semiconductor circuit having plural wiring layers including obtaining various kinds of information such as placement information relating to a plurality of cells or macros of the semiconductor circuit and being mounted onto a circuit board from a storage unit of the computer; comparing a driving capacity of a subject cell or macro, which is contained in the obtained information, and a resistance of wiring for connecting the subject cell or macro with the cell or macro at a connecting destination; and setting up a terminal layer based on a result of the comparing.
Public/Granted literature
Information query
