Invention Grant
- Patent Title: Method for fabricating an electronic component embedded substrate
- Patent Title (中): 电子部件嵌入式基板的制造方法
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Application No.: US11159993Application Date: 2005-06-23
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Publication No.: US07727802B2Publication Date: 2010-06-01
- Inventor: Masahiro Sunohara , Keisuke Ueda
- Applicant: Masahiro Sunohara , Keisuke Ueda
- Applicant Address: JP Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano
- Agency: Ladas & Parry LLP
- Priority: JP2004-194783 20040630
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method for fabricating an electronic component embedded substrate including an electronic component that is embedded within a buildup layer is disclosed. The method includes a first buildup layer lamination step of laminating plural first buildup layers on a core substrate such that the total thickness of the first buildup layers corresponds to the thickness of the electronic component; a cavity formation step of forming a cavity for accommodating the electronic component at the laminated first buildup layers; an accommodating step of accommodating the electronic component within the cavity; and a second buildup layer lamination step of laminating a second buildup layer on the first buildup layers and the electronic component.
Public/Granted literature
- US20060003495A1 Method for fabricating an electronic component embedded substrate Public/Granted day:2006-01-05
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