Invention Grant
- Patent Title: Method for forming fine pattern by spacer patterning technology
- Patent Title (中): 通过间隔图案化技术形成精细图案的方法
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Application No.: US12164754Application Date: 2008-06-30
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Publication No.: US07727889B2Publication Date: 2010-06-01
- Inventor: Ik Soo Choi , Sung Yoon Cho
- Applicant: Ik Soo Choi , Sung Yoon Cho
- Applicant Address: KR Icheon-si
- Assignee: Hynix Semiconductor Inc
- Current Assignee: Hynix Semiconductor Inc
- Current Assignee Address: KR Icheon-si
- Agency: Marshall, Gerstein & Borun LLP
- Priority: KR10-2008-0040098 20080429
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
In a method for forming a fine pattern, a target layer to be patterned is formed on a semiconductor substrate and a polysilicon layer is formed on the target layer. A partition is then formed on the polysilicon layer with an amorphous carbon layer pattern. A spacer is attached to a sidewall of the partition. Thereafter, the spacer is divided into bar patterns by selectively removing the partition. A polysilicon layer pattern is formed by selectively etching a portion of the poly silicon layer exposed by the divided bar patterns and then a target layer pattern is formed by selectively etching a portion of the target layer exposed by the polysilicon layer pattern.
Public/Granted literature
- US20090269924A1 Method for Forming Fine Pattern by Spacer Patterning Technology Public/Granted day:2009-10-29
Information query
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