Invention Grant
US07727892B2 Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects
有权
用于形成用于集成电路互连的金属 - 金属氧化物蚀刻停止/屏障的方法和装置
- Patent Title: Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects
- Patent Title (中): 用于形成用于集成电路互连的金属 - 金属氧化物蚀刻停止/屏障的方法和装置
-
Application No.: US10255930Application Date: 2002-09-25
-
Publication No.: US07727892B2Publication Date: 2010-06-01
- Inventor: Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
- Applicant: Xiaorong Morrow , Jihperng Leu , Markus Kuhn , Jose A. Maiz
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/311
- IPC: H01L21/311

Abstract:
Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.
Public/Granted literature
Information query
IPC分类: